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ds05-50219-1e fujitsu semiconductor data sheet stacked mcp (multi-chip package) flash memory & sram cmos 32 m ( 8/ 16) flash memory & 4 m ( 8/ 16) static ram mb84vd2218xea/2218xeh- 70/85 / 90 mb84vd2219xea/2218xeh- 70/85 / 90 n n n n features ? power supply voltage of 2.7 v to 3.3 v ? high performance 70 ns/85 ns/90 ns maximum access time (flash) 70 ns/85 ns maximum access time (sram) ? operating temperature - 25 c to + 85 c ? package 71 - ball bga (continued) n n n n product line up n n n n pac k ag e flash memory sram -70 -85 -90 -70 -85/-90 power supply voltage (v) v cc f* = 3.0 v v cc s* = 3.0 v max address access time (ns) 70 85 90 70 85 max ce access time (ns) 70 85 90 70 85 max oe access time (ns) 30 35 40 35 45 + 0.3 v - 0.3 v + 0.3 v - 0.3 v 71-ball plastic bga (bga-71p-m02)
mb84vd2218xea/h/2219xea/h -70/85/90 2 (continued) - flash memory ? simultaneous read/write operations (dual bank) multiple devices available with different bank sizes (refer to n pin description) host system can program or erase in one bank, then immediately and simultaneously read from the other bank zero latency between read and write operations read-while-erase read-while-program ? minimum 100,000 write/erase cycles ? sector erase architecture eight 4 k words and sixty three 32 k words. any combination of sectors can be concurrently erased. also supports full chip erase. ? boot code sector architecture mb84vd2218x : top sector mb84vd2219x : bottom sector ? embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector ? embedded program tm * algorithms automatically writes and verifies data at specified address ? data polling and toggle bit feature for detection of program or erase cycle completion ? ready-busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, automatically switch themselves to low power mode. ? low v cc write inhibit 2.5 v ? hidden rom (hi-rom) region 64 k byte of hi-rom, accessible through a new hi-rom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ? wp /acc input pin at v il , allows protection of boot sectors, regardless of sector protection/unprotection status (mb84vd2218xea/h : sa69, sa70 mb84vd2219xea/h : sa0, sa1) at v ih , allows removal of boot sector protection at v acc , program time will reduce by 40 % . ? erase suspend/resume suspends the erase operation to allow a read in another sector within the same device ? please refer to mbm29dl32xte/be datasheet in detailed function - sram ? power dissipation operating : 40 ma max standby : 7 m a max ? power down features using ce1 s and ce2s ? data retention supply voltage : 1.5 v to 3.3 v ? ce1 s and ce2s chip select ? byte data control : lb s (dq 0 -dq 7 ) , ub s (dq 8 -dq 15 ) * : embedded erase tm and embedded program tm are trademarks of advanced micro devices , inc.
mb84vd2218xea/h/2219xea/h -70/85/90 3 n n n n pin assignment (top view) marking side (bga-71p-m02) a8 b8 n.c. n.c. n.c. n.c. a7 b7 c7 d7 e7 f7 g7 h7 dq 15 / a -1 j7 k7 c6 d6 e6 f6 g6 h6 j6 k6 a 8 a 19 a 9 a 10 dq 6 dq 13 dq 12 dq 5 c5 d5 e5 h5 j5 k5 we ce2s a 20 dq 4 v cc s cios c4 d4 e4 h4 j4 k4 wp/ acc reset ry/by dq 3 v cc fdq 11 c3 d3 e3 f3 g3 h3 j3 k3 lbs ubs a 18 a 17 dq 1 dq 9 dq 10 dq 2 c2 d2 e2 f2 g2 h2 j2 k2 l2 m2 a 7 a2 n.c. a1 n.c. b1 n.c. a 6 a 5 a 4 v ss oe dq 0 dq 8 l7 l8 m7 a 11 a 12 a 13 a 14 sa dq 7 dq 14 n.c. n.c. d8 e8 a 15 n.c. f8 n.c. g8 h8 a 16 ciof j8 v ss d1 a 3 e1 a 2 f1 a 1 g1 a 0 h1 cef j1 ce1s m8 n.c. n.c. l1 n.c. m1 n.c. n.c. n.c.
mb84vd2218xea/h/2219xea/h -70/85/90 4 n n n n pin description pin function input/output a 17 to a 0 address inputs (common) i a 20 to a 18 , a- 1 address input (flash) i sa address input (sram) i dq 15 to dq 0 data inputs/outputs (common) i/o ce f chip enable (flash) i ce1 s chip enable (sram) i ce2s chip enable (sram) i oe output enable (common) i we write enable (common) i ry/by ready/busy outputs (flash) open drain output o ub s upper byte control (sram) i lb s lower byte control (sram) i ciof i/o configuration (flash) ciof = vccf is word mode ( 16) , ciof = vss byte mode ( 8) i cios i/o configuration (sram) cios = vccs is word mode ( 16) , cios = vss is byte mode ( 8) i reset hardware reset pin/sector protection unlock (flash) i wp /acc write protect/acceleration (flash) i n.c. no internal connection ? v ss device ground (common) power v cc f device power supply (flash) power v cc s device power supply (sram) power
mb84vd2218xea/h/2219xea/h -70/85/90 5 n n n n block diagram v cc fv ss v cc sv ss ry/by a 0 to a 20 a 0 to a 17 a 20 to a 0 wp/acc reset cef ciof a -1 lbs sa ubs we oe ce1s ce2s cios 32 m bit flash memory 4 m bit static ram dq 15 /a -1 to dq 0 dq 15 /a -1 to dq 0 dq 15 to dq 0
mb84vd2218xea/h/2219xea/h -70/85/90 6 n n n n device bus operation user bus operations table (flash = = = = word mode; ciof = = = = vccf, sram = = = = word mode; cios = = = = vccs) legend : l = v il , h = v ih , x = v il or v ih . see n dc characteristics for voltage levels. *1: other operations not indicated in this column are prohibited. *2: we can be v il if oe is v il , oe at v ih initiates the write operations. *3: do not apply ce f = v il , ce1 s = v il and ce2s = v ih all at once. *4: also used for the extended sector group protections. *5: wp /acc = v il ; protection of boot sectors. wp /acc = v ih ; removal of boot sectors protection. wp /acc = v acc (9 v) ; program time will be reduced by 40 % . *6: sa : dont care or open. operation * 1, * 3 ce fce1 sce2s oe we sa * 6 lb sub sdq 0 to dq 7 dq 8 to dq 15 reset wp / acc * 5 full standby h hx x x x x x high-z high-z h x xl output disable hl h h h x x x high-z high-z hx x x x h h high-z high-z l hx h h x x x high-z high-z xl read from flash * 2 l hx lhxxx d out d out hx xl write to flash l hx hlxxx d in d in hx xl read from sram h l h l h x ll d out d out hx h l high-z d out lh d out high-z write to sram h l h x l x ll d in d in hx h l high-z d in lh d in high-z temporary sector group unprotection * 4 x x x xxxxx x x v id x flash hardware reset x hx x x x x x high-z high-z l x xl boot block sector write protection x x x xxxxx x x x l
mb84vd2218xea/h/2219xea/h -70/85/90 7 user bus operations table (flash = = = = word mode; ciof = = = = v ccf , sram = = = = byte mode; cios = = = = v ss ) legend : l = v il , h = v ih , x = v il or v ih . see n dc characteristics for voltage levels. *1: other operations not indicated in this column are prohibited. *2: we can be v il if oe is v il , oe at v ih initiates the write operations. *3: do not apply ce f = v il , ce1 s = v il and ce2s = v ih all at once. *4: also used for the extended sector group protections. *5: wp /acc = v il ; protection of boot sectors. wp /acc = v ih ; removal of boot sectors protection. wp /acc = v acc (9 v) ; program time will be reduced by 40 % . *6: lb s , ub s : dont care or open. operation * 1, * 3 ce fce1 sce2s oe we sa lb s * 6 ub s * 6 dq 0 to dq 7 dq 8 to dq 15 reset wp / acc * 5 full standby h hx x x x x x high-z high-z h x xl output disable hl h h h x x x high-z high-z hx x x x h h high-z high-z l hx h h x x x high-z high-z xl read from flash * 2 l hx lhxxx d out d out hx xl write to flash l hx hlxxx d in d in hx xl read from sram h l h l h sa x x d out high-z h x write to sram h l h x l sa x x d in high-z h x temporary sector group unprotection * 4 x x x xxxxx x x v id x flash hardware reset x hx x x x x x high-z high-z l x xl boot block sector write protection x x x xxxxx x x x l
mb84vd2218xea/h/2219xea/h -70/85/90 8 user bus operations table (flash = = = = byte mode; ciof = = = = v ss , sram = = = = byte mode; cios = = = = v ss ) legend : l = v il , h = v ih , x = v il or v ih . see n dc characteristics for voltage levels. *1: other operations not indicated in this column are prohibited. *2: we can be v il if oe is v il , oe at v ih initiates the write operations. *3: do not apply ce f = v il , ce1 s = v il and ce2s = v ih all at once. *4: also used for the extended sector group protections. *5: wp /acc = v il ; protection of boot sectors. wp /acc = v ih ; removal of boot sectors protection. wp /acc = v acc (9 v) ; program time will be reduced by 40 % . *6: lb s , ub s : dont care or open. operation * 1, * 3 ce fce1 sce2sdq 15 /a -1 oe we sa lb s * 6 ub s * 6 dq 0 to dq 7 dq 8 to dq 14 reset wp / acc * 5 full standby h hx x xxx x x high-zhigh-z h x xl output disable hl h x h h x x x high-z high-z hx x xxx h h high-zhigh-z l hx a -1 h h x x x high-z high-z xl read from flash * 2 l hx a -1 lhx x x d out xhx xl write to flash l hx a -1 hlx x x d in xhx xl read from sram h l h x l h sa x x d out high-z h x write to sram h l h x x l sa x x d in high-z h x temporary sector group unprotection * 4 x x x x xxx x x x x v id x flash hardware reset x hx x xxx x x high-zhigh-z l x xl boot block sector write protection x x x x xxx x x x x x l
mb84vd2218xea/h/2219xea/h -70/85/90 9 n n n n flexible sector-erase architecture on flash memory ? eight 4 k words, and sixty three 32 k words. ? individual-sector, multiple-sector, or bulk-erase capability. (continued) word mode 1fffffh 1ff000h 1fe000h 1fd000h 1fc000h 1fb000h 1fa000h 1f9000h 1f8000h 1f0000h 1e8000h 1e0000h 1d8000h 1d0000h 1c8000h 1c0000h 1b8000h 1b0000h 1a8000h 1a0000h 198000h 190000h 188000h 180000h 178000h 170000h 168000h 160000h 158000h 150000h 148000h 140000h 138000h 130000h 128000h 120000h 118000h 110000h 108000h 100000h 0f8000h 0f0000h 0e8000h 0e0000h 0d8000h 0d0000h 0c8000h 0c0000h 0b8000h 0b0000h 0a8000h 0a0000h 098000h 090000h 088000h 080000h 078000h 070000h 068000h 060000h 058000h 050000h 048000h 040000h 038000h 030000h 028000h 020000h 018000h 010000h 008000h 000000h byte mode 3fffffh 3fe000h 3fc000h 3fa000h 3f8000h 3f6000h 3f4000h 3f2000h 3f0000h 3e0000h 3d0000h 3c0000h 3b0000h 3a0000h 390000h 380000h 370000h 360000h 350000h 340000h 330000h 320000h 310000h 300000h 2f0000h 2e0000h 2d0000h 2c0000h 2b0000h 2a0000h 290000h 280000h 270000h 260000h 250000h 240000h 230000h 220000h 210000h 200000h 1f0000h 1e0000h 1d0000h 1c0000h 1b0000h 1a0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0f0000h 0e0000h 0d0000h 0c0000h 0b0000h 0a0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h bank 1 mb84vd22182ea/h bank 1 mb84vd22183ea/h bank 1 mb84vd22184ea/h bank 2 mb84vd22182ea/h bank 2 mb84vd22183ea/h bank 2 mb84vd22184ea/h sa70 : 8 kb (4 kw) sa69 : 8 kb (4 kw) sa68 : 8 kb (4 kw) sa67 : 8 kb (4 kw) sa66 : 8 kb (4 kw) sa65 : 8 kb (4 kw) sa64 : 8 kb (4 kw) sa63 : 8 kb (4 kw) sa62 : 64 kb (32 kw) sa61 : 64 kb (32 kw) sa60 : 64 kb (32 kw) sa59 : 64 kb (32 kw) sa58 : 64 kb (32 kw) sa57 : 64 kb (32 kw) sa56 : 64 kb (32 kw) sa55 : 64 kb (32 kw) sa54 : 64 kb (32 kw) sa53 : 64 kb (32 kw) sa52 : 64 kb (32 kw) sa51 : 64 kb (32 kw) sa50 : 64 kb (32 kw) sa49 : 64 kb (32 kw) sa48 : 64 kb (32 kw) sa47 : 64 kb (32 kw) sa46 : 64 kb (32 kw) sa45 : 64 kb (32 kw) sa44 : 64 kb (32 kw) sa43 : 64 kb (32 kw) sa42 : 64 kb (32 kw) sa41 : 64 kb (32 kw) sa40 : 64 kb (32 kw) sa39 : 64 kb (32 kw) sa38 : 64 kb (32 kw) sa37 : 64 kb (32 kw) sa36 : 64 kb (32 kw) sa35 : 64 kb (32 kw) sa34 : 64 kb (32 kw) sa33 : 64 kb (32 kw) sa32 : 64 kb (32 kw) sa31 : 64 kb (32 kw) sa30 : 64 kb (32 kw) sa29 : 64 kb (32 kw) sa28 : 64 kb (32 kw) sa27 : 64 kb (32 kw) sa26 : 64 kb (32 kw) sa25 : 64 kb (32 kw) sa24 : 64 kb (32 kw) sa23 : 64 kb (32 kw) sa22 : 64 kb (32 kw) sa21 : 64 kb (32 kw) sa20 : 64 kb (32 kw) sa19 : 64 kb (32 kw) sa18 : 64 kb (32 kw) sa17 : 64 kb (32 kw) sa16 : 64 kb (32 kw) sa15 : 64 kb (32 kw) sa14 : 64 kb (32 kw) sa13 : 64 kb (32 kw) sa12 : 64 kb (32 kw) sa11 : 64 kb (32 kw) sa10 : 64 kb (32 kw) sa9 : 64 kb (32 kw) sa8 : 64 kb (32 kw) sa7 : 64 kb (32 kw) sa6 : 64 kb (32 kw) sa5 : 64 kb (32 kw) sa4 : 64 kb (32 kw) sa3 : 64 kb (32 kw) sa2 : 64 kb (32 kw) sa1 : 64 kb (32 kw) sa0 : 64 kb (32 kw) mb84vd2218xea/h sector architecture (top boot block)
mb84vd2218xea/h/2219xea/h -70/85/90 10 (continued) word mode 1fffffh 1f8000h 1f0000h 1e8000h 1e0000h 1d8000h 1d0000h 1c8000h 1c0000h 1b8000h 1b0000h 1a8000h 1a0000h 198000h 190000h 188000h 180000h 178000h 170000h 168000h 160000h 158000h 150000h 148000h 140000h 138000h 130000h 128000h 120000h 118000h 110000h 108000h 100000h 0f8000h 0f0000h 0e8000h 0e0000h 0d8000h 0d0000h 0c8000h 0c0000h 0b8000h 0b0000h 0a8000h 0a0000h 098000h 090000h 088000h 080000h 078000h 070000h 068000h 060000h 058000h 050000h 048000h 040000h 038000h 030000h 028000h 020000h 018000h 010000h 008000h 007000h 006000h 005000h 004000h 003000h 002000h 001000h 000000h byte mode 3fffffh 3f0000h 3e0000h 3d0000h 3c0000h 3b0000h 3a0000h 390000h 380000h 370000h 360000h 350000h 340000h 330000h 320000h 310000h 300000h 2f0000h 2e0000h 2d0000h 2c0000h 2b0000h 2a0000h 290000h 280000h 270000h 260000h 250000h 240000h 230000h 220000h 210000h 200000h 1f0000h 1e0000h 1d0000h 1c0000h 1b0000h 1a0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0f0000h 0e0000h 0d0000h 0c0000h 0b0000h 0a0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 00e000h 00c000h 00a000h 008000h 006000h 004000h 002000h 000000h bank 1 mb84vd22192ea/h bank 1 mb84vd22193ea/h bank 1 mb84vd22194ea/h bank 2 mb84vd22192ea/h bank 2 mb84vd22193ea/h bank 2 mb84vd22194ea/h sa70 : 64 kb (32 kw) sa69 : 64 kb (32 kw) sa68 : 64 kb (32 kw) sa67 : 64 kb (32 kw) sa66 : 64 kb (32 kw) sa65 : 64 kb (32 kw) sa64 : 64 kb (32 kw) sa63 : 64 kb (32 kw) sa62 : 64 kb (32 kw) sa61 : 64 kb (32 kw) sa60 : 64 kb (32 kw) sa59 : 64 kb (32 kw) sa58 : 64 kb (32 kw) sa57 : 64 kb (32 kw) sa56 : 64 kb (32 kw) sa55 : 64 kb (32 kw) sa54 : 64 kb (32 kw) sa53 : 64 kb (32 kw) sa52 : 64 kb (32 kw) sa51 : 64 kb (32 kw) sa50 : 64 kb (32 kw) sa49 : 64 kb (32 kw) sa48 : 64 kb (32 kw) sa47 : 64 kb (32 kw) sa46 : 64 kb (32 kw) sa45 : 64 kb (32 kw) sa44 : 64 kb (32 kw) sa43 : 64 kb (32 kw) sa42 : 64 kb (32 kw) sa41 : 64 kb (32 kw) sa40 : 64 kb (32 kw) sa39 : 64 kb (32 kw) sa38 : 64 kb (32 kw) sa37 : 64 kb (32 kw) sa36 : 64 kb (32 kw) sa35 : 64 kb (32 kw) sa34 : 64 kb (32 kw) sa33 : 64 kb (32 kw) sa32 : 64 kb (32 kw) sa31 : 64 kb (32 kw) sa30 : 64 kb (32 kw) sa29 : 64 kb (32 kw) sa28 : 64 kb (32 kw) sa27 : 64 kb (32 kw) sa26 : 64 kb (32 kw) sa25 : 64 kb (32 kw) sa24 : 64 kb (32 kw) sa23 : 64 kb (32 kw) sa22 : 64 kb (32 kw) sa21 : 64 kb (32 kw) sa20 : 64 kb (32 kw) sa19 : 64 kb (32 kw) sa18 : 64 kb (32 kw) sa17 : 64 kb (32 kw) sa16 : 64 kb (32 kw) sa15 : 64 kb (32 kw) sa14 : 64 kb (32 kw) sa13 : 64 kb (32 kw) sa12 : 64 kb (32 kw) sa11 : 64 kb (32 kw) sa10 : 64 kb (32 kw) sa9 : 64 kb (32 kw) sa8 : 64 kb (32 kw) sa7 : 8 kb (4 kw) sa6 : 8 kb (4 kw) sa5 : 8 kb (4 kw) sa4 : 8 kb (4 kw) sa3 : 8 kb (4 kw) sa2 : 8 kb (4 kw) sa1 : 8 kb (4 kw) sa0 : 8 kb (4 kw) mb84vd2219xea/h sector architecture (bottom boot block)
mb84vd2218xea/h/2219xea/h -70/85/90 11 sector address table (mb84vd22182ea/h) (continued) ba : bank address bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa0000000xxxx 000000h to 00ffffh 000000h to 007fffh sa1000001xxxx 010000h to 01ffffh 008000h to 00ffffh sa2000010xxxx 020000h to 02ffffh 010000h to 017fffh sa3000011xxxx 030000h to 03ffffh 018000h to 01ffffh sa4000100xxxx 040000h to 04ffffh 020000h to 027fffh sa5000101xxxx 050000h to 05ffffh 028000h to 02ffffh sa6000110xxxx 060000h to 06ffffh 030000h to 037fffh sa7000111xxxx 070000h to 07ffffh 038000h to 03ffffh sa8001000xxxx 080000h to 08ffffh 040000h to 047fffh sa9001001xxxx 090000h to 09ffffh 048000h to 04ffffh sa10001010xxxx0a0000h to 0affffh05 0000h to 057fffh sa11001011xxxx0b0000h to 0bffffh05 8000h to 05ffffh sa12001100xxxx0c00 00h to 0cffffh 060000h to 067fffh sa13001101xxxx0d00 00h to 0dffffh 068000h to 06ffffh sa14001110xxxx0e0000h to 0effffh07 0000h to 077fffh sa15001111xxxx0f00 00h to 0fffffh 078000h to 07ffffh sa16010000xxxx 100000h to 10ffffh 080000h to 087fffh sa17010001xxxx 110000h to 11ffffh 088000h to 08ffffh sa18010010xxxx 120000h to 12ffffh 090000h to 097fffh sa19010011xxxx 130000h to 13ffffh 098000h to 09ffffh sa20010100xxxx 140000h to 14ffffh 0a0000h to 0a7fffh sa21010101xxxx 150000h to 15ffffh 0a8000h to 0affffh sa22010110xxxx 160000h to 16ffffh 0b0000h to 0b7fffh sa23010111xxxx 170000h to 17ffffh 0b8000h to 0bffffh sa24011000xxxx 180000h to 18ffffh 0c0000h to 0c7fffh sa25011001xxxx 190000h to 19ffffh 0c8000h to 0cffffh sa26011010xxxx1a0000h to 1affffh0d 0000h to 0d7fffh sa27011011xxxx1b0000h to 1bffffh0d 8000h to 0dffffh sa28011100xxxx1c00 00h to 1cffffh 0e0000h to 0e7fffh sa29011101xxxx1d00 00h to 1dffffh 0e8000h to 0effffh sa30011110xxxx1e0000h to 1effffh0f 0000h to 0f7fffh sa31011111xxxx1f00 00h to 1fffffh 0f8000h to 0fffffh
mb84vd2218xea/h/2219xea/h -70/85/90 12 (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa32100000xxxx 200000h to 20ffffh 100000h to 107fffh sa33100001xxxx 210000h to 21ffffh 108000h to 10ffffh sa34100010xxxx 220000h to 22ffffh 110000h to 117fffh sa35100011xxxx 230000h to 23ffffh 118000h to 11ffffh sa36100100xxxx 240000h to 24ffffh 120000h to 127fffh sa37100101xxxx 250000h to 25ffffh 128000h to 12ffffh sa38100110xxxx 260000h to 26ffffh 130000h to 137fffh sa39100111xxxx 270000h to 27ffffh 138000h to 13ffffh sa40101000xxxx 280000h to 28ffffh 140000h to 147fffh sa41101001xxxx 290000h to 29ffffh 148000h to 14ffffh sa42101010xxxx2a0000h to 2affffh15 0000h to 157fffh sa43101011xxxx2b0000h to 2bffffh15 8000h to 15ffffh sa44101100xxxx2c00 00h to 2cffffh 160000h to 167fffh sa45101101xxxx2d00 00h to 2dffffh 168000h to 16ffffh sa46101110xxxx2e0000h to 2effffh17 0000h to 177fffh sa47101111xxxx2f00 00h to 2fffffh 178000h to 17ffffh sa48110000xxxx 300000h to 30ffffh 180000h to 187fffh sa49110001xxxx 310000h to 31ffffh 188000h to 18ffffh sa50110010xxxx 320000h to 32ffffh 190000h to 197fffh sa51110011xxxx 330000h to 33ffffh 198000h to 19ffffh sa52110100xxxx 340000h to 34ffffh 1a0000h to 1a7fffh sa53110101xxxx 350000h to 35ffffh 1a8000h to 1affffh sa54110110xxxx 360000h to 36ffffh 1b0000h to 1b7fffh sa55110111xxxx 370000h to 37ffffh 1b8000h to 1bffffh bank 1 sa56111000xxxx 380000h to 38ffffh 1c0000h to 1c7fffh sa57111001xxxx 390000h to 39ffffh 1c8000h to 1cffffh sa58111010xxxx3a0000h to 3affffh1d 0000h to 1d7fffh sa59111011xxxx3b0000h to 3bffffh1d 8000h to 1dffffh sa60111100xxxx3c00 00h to 3cffffh 1e0000h to 1e7fffh sa61111101xxxx3d00 00h to 3dffffh 1e8000h to 1effffh sa62111110xxxx3e0000h to 3effffh1f 0000h to 1f7fffh sa63111111000x3f0 000h to 3f1fffh 1f8000h to 1f8fffh sa64111111001x3f2 000h to 3f3fffh 1f9000h to 1f9fffh sa65111111010x3f4 000h to 3f5fffh 1fa000h to 1fafffh
mb84vd2218xea/h/2219xea/h -70/85/90 13 (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 1 sa66111111011x3f6 000h to 3f7fffh 1fb000h to 1fbfffh sa67111111100x3f8 000h to 3f9fffh 1fc000h to 1fcfffh sa68111111101x3fa 000h to 3fafffh 1fd000h to 1fdfffh sa69111111110x3fc 000h to 3fcfffh 1fe000h to 1fefffh sa70111111111x3fe000h to 3fffffh1ff000h to 1fffffh
mb84vd2218xea/h/2219xea/h -70/85/90 14 sector address table (mb84vd22192ea/h) (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 1 sa0000000000x000 000h to 001fffh 000000h to 000fffh sa1000000001x002 000h to 003fffh 001000h to 001fffh sa2000000010x004 000h to 005fffh 002000h to 002fffh sa3000000011x006 000h to 007fffh 003000h to 003fffh sa4000000100x008 000h to 009fffh 004000h to 004fffh sa5000000101x00a 000h to 00bfffh 005000h to 005fffh sa6000000110x00c 000h to 00dfffh 006000h to 006fffh sa7000000111x00e000h to 00ffffh00 7000h to 007fffh sa8000001xxxx 010000h to 01ffffh 008000h to 00ffffh sa9000010xxxx 020000h to 02ffffh 010000h to 017fffh sa10000011xxxx 030000h to 03ffffh 018000h to 01ffffh sa11000100xxxx 040000h to 04ffffh 020000h to 027fffh sa12000101xxxx 050000h to 05ffffh 028000h to 02ffffh sa13000110xxxx 060000h to 06ffffh 030000h to 037fffh sa14000111xxxx 070000h to 07ffffh 038000h to 03ffffh bank 2 sa15001000xxxx 080000h to 08ffffh 040000h to 047fffh sa16001001xxxx 090000h to 09ffffh 048000h to 04ffffh sa17001010xxxx0a0000h to 0affffh05 0000h to 057fffh sa18001011xxxx0b0000h to 0bffffh05 8000h to 05ffffh sa19001100xxxx0c00 00h to 0cffffh 060000h to 067fffh sa20001101xxxx0d00 00h to 0dffffh 068000h to 06ffffh sa21001110xxxx0e0000h to 0effffh07 0000h to 077fffh sa22001111xxxx0f00 00h to 0fffffh 078000h to 07ffffh sa23010000xxxx 100000h to 10ffffh 080000h to 087fffh sa24010001xxxx 110000h to 11ffffh 088000h to 08ffffh sa25010010xxxx 120000h to 12ffffh 090000h to 097fffh sa26010011xxxx 130000h to 13ffffh 098000h to 09ffffh sa27010100xxxx 140000h to 14ffffh 0a0000h to 0a7fffh sa28010101xxxx 150000h to 15ffffh 0a8000h to 0affffh sa29010110xxxx 160000h to 16ffffh 0b0000h to 0b7fffh sa30010111xxxx 170000h to 17ffffh 0b8000h to 0bffffh sa31011000xxxx 180000h to 18ffffh 0c0000h to 0c7fffh
mb84vd2218xea/h/2219xea/h -70/85/90 15 (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa32011001xxxx 190000h to 19ffffh 0c8000h to 0cffffh sa33011010xxxx1a0000h to 1affffh0d 0000h to 0d7fffh sa34011011xxxx1b0000h to 1bffffh0d 8000h to 0dffffh sa35011100xxxx1c00 00h to 1cffffh 0e0000h to 0e7fffh sa36011101xxxx1d00 00h to 1dffffh 0e8000h to 0effffh sa37011110xxxx1e0000h to 1effffh0f 0000h to 0f7fffh sa38011111xxxx1f00 00h to 1fffffh 0f8000h to 0fffffh sa39100000xxxx 200000h to 20ffffh 100000h to 107fffh sa40100001xxxx 210000h to 21ffffh 108000h to 10ffffh sa41100010xxxx 220000h to 22ffffh 110000h to 117fffh sa42100011xxxx 230000h to 23ffffh 118000h to 11ffffh sa43100100xxxx 240000h to 24ffffh 120000h to 127fffh sa44100101xxxx 250000h to 25ffffh 128000h to 12ffffh sa45100110xxxx 260000h to 26ffffh 130000h to 137fffh sa46100111xxxx 270000h to 27ffffh 138000h to 13ffffh sa47101000xxxx 280000h to 28ffffh 140000h to 147fffh sa48101001xxxx 290000h to 29ffffh 148000h to 14ffffh sa49101010xxxx2a0000h to 2affffh15 0000h to 157fffh sa50101011xxxx2b0000h to 2bffffh15 8000h to 15ffffh sa51101100xxxx2c00 00h to 2cffffh 160000h to 167fffh sa52101101xxxx2d00 00h to 2dffffh 168000h to 16ffffh sa53101110xxxx2e0000h to 2effffh17 0000h to 177fffh sa54101111xxxx2f00 00h to 2fffffh 178000h to 17ffffh sa55110000xxxx 300000h to 30ffffh 180000h to 187fffh sa56110001xxxx 310000h to 31ffffh 188000h to 18ffffh sa57110010xxxx 320000h to 32ffffh 190000h to 197fffh sa58110011xxxx 330000h to 33ffffh 198000h to 19ffffh sa59110100xxxx 340000h to 34ffffh 1a0000h to 1a7fffh sa60110101xxxx 350000h to 35ffffh 1a8000h to 1affffh sa61110110xxxx 360000h to 36ffffh 1b0000h to 1b7fffh sa62110111xxxx 370000h to 37ffffh 1b8000h to 1bffffh sa63111000xxxx 380000h to 38ffffh 1c0000h to 1c7fffh sa64111001xxxx 390000h to 39ffffh 1c8000h to 1cffffh sa65111010xxxx3a0000h to 3affffh1d 0000h to 1d7fffh
mb84vd2218xea/h/2219xea/h -70/85/90 16 (continued) ba : bank address bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa66111011xxxx3b0000h to 3bffffh1d 8000h to 1dffffh sa67111100xxxx3c00 00h to 3cffffh 1e0000h to 1e7fffh sa68111101xxxx3d00 00h to 3dffffh 1e8000h to 1effffh sa69111110xxxx3e0000h to 3effffh1f 0000h to 1f7fffh sa70111111xxxx3f00 00h to 3fffffh 1f8000h to 1fffffh
mb84vd2218xea/h/2219xea/h -70/85/90 17 sector address table (mb84vd22183ea/h) (continued) ba : bank address bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa0000000xxxx 000000h to 00ffffh 000000h to 007fffh sa1000001xxxx 010000h to 01ffffh 008000h to 00ffffh sa2000010xxxx 020000h to 02ffffh 010000h to 017fffh sa3000011xxxx 030000h to 03ffffh 018000h to 01ffffh sa4000100xxxx 040000h to 04ffffh 020000h to 027fffh sa5000101xxxx 050000h to 05ffffh 028000h to 02ffffh sa6000110xxxx 060000h to 06ffffh 030000h to 037fffh sa7000111xxxx 070000h to 07ffffh 038000h to 03ffffh sa8001000xxxx 080000h to 08ffffh 040000h to 047fffh sa9001001xxxx 090000h to 09ffffh 048000h to 04ffffh sa10001010xxxx0a0000h to 0affffh05 0000h to 057fffh sa11001011xxxx0b0000h to 0bffffh05 8000h to 05ffffh sa12001100xxxx0c00 00h to 0cffffh 060000h to 067fffh sa13001101xxxx0d00 00h to 0dffffh 068000h to 06ffffh sa14001110xxxx0e0000h to 0effffh07 0000h to 077fffh sa15001111xxxx0f00 00h to 0fffffh 078000h to 07ffffh sa16010000xxxx 100000h to 10ffffh 080000h to 087fffh sa17010001xxxx 110000h to 11ffffh 088000h to 08ffffh sa18010010xxxx 120000h to 12ffffh 090000h to 097fffh sa19010011xxxx 130000h to 13ffffh 098000h to 09ffffh sa20010100xxxx 140000h to 14ffffh 0a0000h to 0a7fffh sa21010101xxxx 150000h to 15ffffh 0a8000h to 0affffh sa22010110xxxx 160000h to 16ffffh 0b0000h to 0b7fffh sa23010111xxxx 170000h to 17ffffh 0b8000h to 0bffffh sa24011000xxxx 180000h to 18ffffh 0c0000h to 0c7fffh sa25011001xxxx 190000h to 19ffffh 0c8000h to 0cffffh sa26011010xxxx1a0000h to 1affffh0d 0000h to 0d7fffh sa27011011xxxx1b0000h to 1bffffh0d 8000h to 0dffffh sa28011100xxxx1c00 00h to 1cffffh 0e0000h to 0e7fffh sa29011101xxxx1d00 00h to 1dffffh 0e8000h to 0effffh sa30011110xxxx1e0000h to 1effffh0f 0000h to 0f7fffh sa31011111xxxx1f00 00h to 1fffffh 0f8000h to 0fffffh
mb84vd2218xea/h/2219xea/h -70/85/90 18 (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa32100000xxxx 200000h to 20ffffh 100000h to 107fffh sa33100001xxxx 210000h to 21ffffh 108000h to 10ffffh sa34100010xxxx 220000h to 22ffffh 110000h to 117fffh sa35100011xxxx 230000h to 23ffffh 118000h to 11ffffh sa36100100xxxx 240000h to 24ffffh 120000h to 127fffh sa37100101xxxx 250000h to 25ffffh 128000h to 12ffffh sa38100110xxxx 260000h to 26ffffh 130000h to 137fffh sa39100111xxxx 270000h to 27ffffh 138000h to 13ffffh sa40101000xxxx 280000h to 28ffffh 140000h to 147fffh sa41101001xxxx 290000h to 29ffffh 148000h to 14ffffh sa42101010xxxx2a0000h to 2affffh15 0000h to 157fffh sa43101011xxxx2b0000h to 2bffffh15 8000h to 15ffffh sa44101100xxxx2c00 00h to 2cffffh 160000h to 167fffh sa45101101xxxx2d00 00h to 2dffffh 168000h to 16ffffh sa46101110xxxx2e0000h to 2effffh17 0000h to 177fffh sa47101111xxxx2f00 00h to 2fffffh 178000h to 17ffffh bank 1 sa48110000xxxx 300000h to 30ffffh 180000h to 187fffh sa49110001xxxx 310000h to 31ffffh 188000h to 18ffffh sa50110010xxxx 320000h to 32ffffh 190000h to 197fffh sa51110011xxxx 330000h to 33ffffh 198000h to 19ffffh sa52110100xxxx 340000h to 34ffffh 1a0000h to 1a7fffh sa53110101xxxx 350000h to 35ffffh 1a8000h to 1affffh sa54110110xxxx 360000h to 36ffffh 1b0000h to 1b7fffh sa55110111xxxx 370000h to 37ffffh 1b8000h to 1bffffh sa56111000xxxx 380000h to 38ffffh 1c0000h to 1c7fffh sa57111001xxxx 390000h to 39ffffh 1c8000h to 1cffffh sa58111010xxxx3a0000h to 3affffh1d 0000h to 1d7fffh sa59111011xxxx3b0000h to 3bffffh1d 8000h to 1dffffh sa60111100xxxx3c00 00h to 3cffffh 1e0000h to 1e7fffh sa61111101xxxx3d00 00h to 3dffffh 1e8000h to 1effffh sa62111110xxxx3e0000h to 3effffh1f 0000h to 1f7fffh sa63111111000x3f0 000h to 3f1fffh 1f8000h to 1f8fffh sa64111111001x3f2 000h to 3f3fffh 1f9000h to 1f9fffh sa65111111010x3f4 000h to 3f5fffh 1fa000h to 1fafffh
mb84vd2218xea/h/2219xea/h -70/85/90 19 (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 1 sa66111111011x3f6 000h to 3f7fffh 1fb000h to 1fbfffh sa67111111100x3f8 000h to 3f9fffh 1fc000h to 1fcfffh sa68111111101x3fa 000h to 3fafffh 1fd000h to 1fdfffh sa69111111110x3fc 000h to 3fcfffh 1fe000h to 1fefffh sa70111111111x3fe000h to 3fffffh1ff000h to 1fffffh
mb84vd2218xea/h/2219xea/h -70/85/90 20 sector address table (mb84vd22193ea/h) (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 1 sa0000000000x000 000h to 001fffh 000000h to 000fffh sa1000000001x002 000h to 003fffh 001000h to 001fffh sa2000000010x004 000h to 005fffh 002000h to 002fffh sa3000000011x006 000h to 007fffh 003000h to 003fffh sa4000000100x008 000h to 009fffh 004000h to 004fffh sa5000000101x00a 000h to 00bfffh 005000h to 005fffh sa6000000110x00c 000h to 00dfffh 006000h to 006fffh sa7000000111x00e000h to 00ffffh00 7000h to 007fffh sa8000001xxxx 010000h to 01ffffh 008000h to 00ffffh sa9000010xxxx 020000h to 02ffffh 010000h to 017fffh sa10000011xxxx 030000h to 03ffffh 018000h to 01ffffh sa11000100xxxx 040000h to 04ffffh 020000h to 027fffh sa12000101xxxx 050000h to 05ffffh 028000h to 02ffffh sa13000110xxxx 060000h to 06ffffh 030000h to 037fffh sa14000111xxxx 070000h to 07ffffh 038000h to 03ffffh sa15001000xxxx 080000h to 08ffffh 040000h to 047fffh sa16001001xxxx 090000h to 09ffffh 048000h to 04ffffh sa17001010xxxx0a0000h to 0affffh05 0000h to 057fffh sa18001011xxxx0b0000h to 0bffffh05 8000h to 05ffffh sa19001100xxxx0c00 00h to 0cffffh 060000h to 067fffh sa20001101xxxx0d00 00h to 0dffffh 068000h to 06ffffh sa21001110xxxx0e0000h to 0effffh07 0000h to 077fffh sa22001111xxxx0f00 00h to 0fffffh 078000h to 07ffffh bank 2 sa23010000xxxx 100000h to 10ffffh 080000h to 087fffh sa24010001xxxx 110000h to 11ffffh 088000h to 08ffffh sa25010010xxxx 120000h to 12ffffh 090000h to 097fffh sa26010011xxxx 130000h to 13ffffh 098000h to 09ffffh sa27010100xxxx 140000h to 14ffffh 0a0000h to 0a7fffh sa28010101xxxx 150000h to 15ffffh 0a8000h to 0affffh sa29010110xxxx 160000h to 16ffffh 0b0000h to 0b7fffh sa30010111xxxx 170000h to 17ffffh 0b8000h to 0bffffh sa31011000xxxx 180000h to 18ffffh 0c0000h to 0c7fffh
mb84vd2218xea/h/2219xea/h -70/85/90 21 (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa32011001xxxx 190000h to 19ffffh 0c8000h to 0cffffh sa33011010xxxx1a0000h to 1affffh0d 0000h to 0d7fffh sa34011011xxxx1b0000h to 1bffffh0d 8000h to 0dffffh sa35011100xxxx1c00 00h to 1cffffh 0e0000h to 0e7fffh sa36011101xxxx1d00 00h to 1dffffh 0e8000h to 0effffh sa37011110xxxx1e0000h to 1effffh0f 0000h to 0f7fffh sa38011111xxxx1f00 00h to 1fffffh 0f8000h to 0fffffh sa39100000xxxx 200000h to 20ffffh 100000h to 107fffh sa40100001xxxx 210000h to 21ffffh 108000h to 10ffffh sa41100010xxxx 220000h to 22ffffh 110000h to 117fffh sa42100011xxxx 230000h to 23ffffh 118000h to 11ffffh sa43100100xxxx 240000h to 24ffffh 120000h to 127fffh sa44100101xxxx 250000h to 25ffffh 128000h to 12ffffh sa45100110xxxx 260000h to 26ffffh 130000h to 137fffh sa46100111xxxx 270000h to 27ffffh 138000h to 13ffffh sa47101000xxxx 280000h to 28ffffh 140000h to 147fffh sa48101001xxxx 290000h to 29ffffh 148000h to 14ffffh sa49101010xxxx2a0000h to 2affffh15 0000h to 157fffh sa50101011xxxx2b0000h to 2bffffh15 8000h to 15ffffh sa51101100xxxx2c00 00h to 2cffffh 160000h to 167fffh sa52101101xxxx2d00 00h to 2dffffh 168000h to 16ffffh sa53101110xxxx2e0000h to 2effffh17 0000h to 177fffh sa54101111xxxx2f00 00h to 2fffffh 178000h to 17ffffh sa55110000xxxx 300000h to 30ffffh 180000h to 187fffh sa56110001xxxx 310000h to 31ffffh 188000h to 18ffffh sa57110010xxxx 320000h to 32ffffh 190000h to 197fffh sa58110011xxxx 330000h to 33ffffh 198000h to 19ffffh sa59110100xxxx 340000h to 34ffffh 1a0000h to 1a7fffh sa60110101xxxx 350000h to 35ffffh 1a8000h to 1affffh sa61110110xxxx 360000h to 36ffffh 1b0000h to 1b7fffh sa62110111xxxx 370000h to 37ffffh 1b8000h to 1bffffh sa63111000xxxx 380000h to 38ffffh 1c0000h to 1c7fffh sa64111001xxxx 390000h to 39ffffh 1c8000h to 1cffffh sa65111010xxxx3a0000h to 3affffh1d 0000h to 1d7fffh
mb84vd2218xea/h/2219xea/h -70/85/90 22 (continued) ba : bank address bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa66111011xxxx3b0000h to 3bffffh1d 8000h to 1dffffh sa67111100xxxx3c00 00h to 3cffffh 1e0000h to 1e7fffh sa68111101xxxx3d00 00h to 3dffffh 1e8000h to 1effffh sa69111110xxxx3e0000h to 3effffh1f 0000h to 1f7fffh sa70111111xxxx3f00 00h to 3fffffh 1f8000h to 1fffffh
mb84vd2218xea/h/2219xea/h -70/85/90 23 sector address table (mb84vd22184ea/e) (continued) ba : bank address bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa0000000xxxx 000000h to 00ffffh 000000h to 007fffh sa1000001xxxx 010000h to 01ffffh 008000h to 00ffffh sa2000010xxxx 020000h to 02ffffh 010000h to 017fffh sa3000011xxxx 030000h to 03ffffh 018000h to 01ffffh sa4000100xxxx 040000h to 04ffffh 020000h to 027fffh sa5000101xxxx 050000h to 05ffffh 028000h to 02ffffh sa6000110xxxx 060000h to 06ffffh 030000h to 037fffh sa7000111xxxx 070000h to 07ffffh 038000h to 03ffffh sa8001000xxxx 080000h to 08ffffh 040000h to 047fffh sa9001001xxxx 090000h to 09ffffh 048000h to 04ffffh sa10001010xxxx0a0000h to 0affffh05 0000h to 057fffh sa11001011xxxx0b0000h to 0bffffh05 8000h to 05ffffh sa12001100xxxx0c00 00h to 0cffffh 060000h to 067fffh sa13001101xxxx0d00 00h to 0dffffh 068000h to 06ffffh sa14001110xxxx0e0000h to 0effffh07 0000h to 077fffh sa15001111xxxx0f00 00h to 0fffffh 078000h to 07ffffh sa16010000xxxx 100000h to 10ffffh 080000h to 087fffh sa17010001xxxx 110000h to 11ffffh 088000h to 08ffffh sa18010010xxxx 120000h to 12ffffh 090000h to 097fffh sa19010011xxxx 130000h to 13ffffh 098000h to 09ffffh sa20010100xxxx 140000h to 14ffffh 0a0000h to 0a7fffh sa21010101xxxx 150000h to 15ffffh 0a8000h to 0affffh sa22010110xxxx 160000h to 16ffffh 0b0000h to 0b7fffh sa23010111xxxx 170000h to 17ffffh 0b8000h to 0bffffh sa24011000xxxx 180000h to 18ffffh 0c0000h to 0c7fffh sa25011001xxxx 190000h to 19ffffh 0c8000h to 0cffffh sa26011010xxxx1a0000h to 1affffh0d 0000h to 0d7fffh sa27011011xxxx1b0000h to 1bffffh0d 8000h to 0dffffh sa28011100xxxx1c00 00h to 1cffffh 0e0000h to 0e7fffh sa29011101xxxx1d00 00h to 1dffffh 0e8000h to 0effffh sa30011110xxxx1e0000h to 1effffh0f 0000h to 0f7fffh sa31011111xxxx1f00 00h to 1fffffh 0f8000h to 0fffffh
mb84vd2218xea/h/2219xea/h -70/85/90 24 (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 1 sa32100000xxxx 200000h to 20ffffh 100000h to 107fffh sa33100001xxxx 210000h to 21ffffh 108000h to 10ffffh sa34100010xxxx 220000h to 22ffffh 110000h to 117fffh sa35100011xxxx 230000h to 23ffffh 118000h to 11ffffh sa36100100xxxx 240000h to 24ffffh 120000h to 127fffh sa37100101xxxx 250000h to 25ffffh 128000h to 12ffffh sa38100110xxxx 260000h to 26ffffh 130000h to 137fffh sa39100111xxxx 270000h to 27ffffh 138000h to 13ffffh sa40101000xxxx 280000h to 28ffffh 140000h to 147fffh sa41101001xxxx 290000h to 29ffffh 148000h to 14ffffh sa42101010xxxx2a0000h to 2affffh15 0000h to 157fffh sa43101011xxxx2b0000h to 2bffffh15 8000h to 15ffffh sa44101100xxxx2c00 00h to 2cffffh 160000h to 167fffh sa45101101xxxx2d00 00h to 2dffffh 168000h to 16ffffh sa46101110xxxx2e0000h to 2effffh17 0000h to 177fffh sa47101111xxxx2f00 00h to 2fffffh 178000h to 17ffffh sa48110000xxxx 300000h to 30ffffh 180000h to 187fffh sa49110001xxxx 310000h to 31ffffh 188000h to 18ffffh sa50110010xxxx 320000h to 32ffffh 190000h to 197fffh sa51110011xxxx 330000h to 33ffffh 198000h to 19ffffh sa52110100xxxx 340000h to 34ffffh 1a0000h to 1a7fffh sa53110101xxxx 350000h to 35ffffh 1a8000h to 1affffh sa54110110xxxx 360000h to 36ffffh 1b0000h to 1b7fffh sa55110111xxxx 370000h to 37ffffh 1b8000h to 1bffffh sa56111000xxxx 380000h to 38ffffh 1c0000h to 1c7fffh sa57111001xxxx 390000h to 39ffffh 1c8000h to 1cffffh sa58111010xxxx3a0000h to 3affffh1d 0000h to 1d7fffh sa59111011xxxx3b0000h to 3bffffh1d 8000h to 1dffffh sa60111100xxxx3c00 00h to 3cffffh 1e0000h to 1e7fffh sa61111101xxxx3d00 00h to 3dffffh 1e8000h to 1effffh sa62111110xxxx3e0000h to 3effffh1f 0000h to 1f7fffh sa63111111000x3f0 000h to 3f1fffh 1f8000h to 1f8fffh sa64111111001x3f2 000h to 3f3fffh 1f9000h to 1f9fffh sa65111111010x3f4 000h to 3f5fffh 1fa000h to 1fafffh
mb84vd2218xea/h/2219xea/h -70/85/90 25 (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 1 sa66111111011x3f6 000h to 3f7fffh 1fb000h to 1fbfffh sa67111111100x3f8 000h to 3f9fffh 1fc000h to 1fcfffh sa68111111101x3fa 000h to 3fafffh 1fd000h to 1fdfffh sa69111111110x3fc 000h to 3fcfffh 1fe000h to 1fefffh sa70111111111x3fe000h to 3fffffh1ff000h to 1fffffh
mb84vd2218xea/h/2219xea/h -70/85/90 26 sector address table (mb84vd22194ea/h) (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 1 sa0000000000x000 000h to 001fffh 000000h to 000fffh sa1000000001x002 000h to 003fffh 001000h to 001fffh sa2000000010x004 000h to 005fffh 002000h to 002fffh sa3000000011x006 000h to 007fffh 003000h to 003fffh sa4000000100x008 000h to 009fffh 004000h to 004fffh sa5000000101x00a 000h to 00bfffh 005000h to 005fffh sa6000000110x00c 000h to 00dfffh 006000h to 006fffh sa7000000111x00e000h to 00ffffh00 7000h to 007fffh sa8000001xxxx 010000h to 01ffffh 008000h to 00ffffh sa9000010xxxx 020000h to 02ffffh 010000h to 017fffh sa10000011xxxx 030000h to 03ffffh 018000h to 01ffffh sa11000100xxxx 040000h to 04ffffh 020000h to 027fffh sa12000101xxxx 050000h to 05ffffh 028000h to 02ffffh sa13000110xxxx 060000h to 06ffffh 030000h to 037fffh sa14000111xxxx 070000h to 07ffffh 038000h to 03ffffh sa15001000xxxx 080000h to 08ffffh 040000h to 047fffh sa16001001xxxx 090000h to 09ffffh 048000h to 04ffffh sa17001010xxxx0a0000h to 0affffh05 0000h to 057fffh sa18001011xxxx0b0000h to 0bffffh05 8000h to 05ffffh sa19001100xxxx0c00 00h to 0cffffh 060000h to 067fffh sa20001101xxxx0d00 00h to 0dffffh 068000h to 06ffffh sa21001110xxxx0e0000h to 0effffh07 0000h to 077fffh sa22001111xxxx0f00 00h to 0fffffh 078000h to 07ffffh sa23010000xxxx 100000h to 10ffffh 080000h to 087fffh sa24010001xxxx 110000h to 11ffffh 088000h to 08ffffh sa25010010xxxx 120000h to 12ffffh 090000h to 097fffh sa26010011xxxx 130000h to 13ffffh 098000h to 09ffffh sa27010100xxxx 140000h to 14ffffh 0a0000h to 0a7fffh sa28010101xxxx 150000h to 15ffffh 0a8000h to 0affffh sa29010110xxxx 160000h to 16ffffh 0b0000h to 0b7fffh sa30010111xxxx 170000h to 17ffffh 0b8000h to 0bffffh sa31011000xxxx 180000h to 18ffffh 0c0000h to 0c7fffh
mb84vd2218xea/h/2219xea/h -70/85/90 27 (continued) bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 1 sa32011001xxxx 190000h to 19ffffh 0c8000h to 0cffffh sa33011010xxxx1a0000h to 1affffh0d 0000h to 0d7fffh sa34011011xxxx1b0000h to 1bffffh0d 8000h to 0dffffh sa35011100xxxx1c00 00h to 1cffffh 0e0000h to 0e7fffh sa36011101xxxx1d00 00h to 1dffffh 0e8000h to 0effffh sa37011110xxxx1e0000h to 1effffh0f 0000h to 0f7fffh sa38011111xxxx1f00 00h to 1fffffh 0f8000h to 0fffffh bank 2 sa39100000xxxx 200000h to 20ffffh 100000h to 107fffh sa40100001xxxx 210000h to 21ffffh 108000h to 10ffffh sa41100010xxxx 220000h to 22ffffh 110000h to 117fffh sa42100011xxxx 230000h to 23ffffh 118000h to 11ffffh sa43100100xxxx 240000h to 24ffffh 120000h to 127fffh sa44100101xxxx 250000h to 25ffffh 128000h to 12ffffh sa45100110xxxx 260000h to 26ffffh 130000h to 137fffh sa46100111xxxx 270000h to 27ffffh 138000h to 13ffffh sa47101000xxxx 280000h to 28ffffh 140000h to 147fffh sa48101001xxxx 290000h to 29ffffh 148000h to 14ffffh sa49101010xxxx2a0000h to 2affffh15 0000h to 157fffh sa50101011xxxx2b0000h to 2bffffh15 8000h to 15ffffh sa51101100xxxx2c00 00h to 2cffffh 160000h to 167fffh sa52101101xxxx2d00 00h to 2dffffh 168000h to 16ffffh sa53101110xxxx2e0000h to 2effffh17 0000h to 177fffh sa54101111xxxx2f00 00h to 2fffffh 178000h to 17ffffh sa55110000xxxx 300000h to 30ffffh 180000h to 187fffh sa56110001xxxx 310000h to 31ffffh 188000h to 18ffffh sa57110010xxxx 320000h to 32ffffh 190000h to 197fffh sa58110011xxxx 330000h to 33ffffh 198000h to 19ffffh sa59110100xxxx 340000h to 34ffffh 1a0000h to 1a7fffh sa60110101xxxx 350000h to 35ffffh 1a8000h to 1affffh sa61110110xxxx 360000h to 36ffffh 1b0000h to 1b7fffh sa62110111xxxx 370000h to 37ffffh 1b8000h to 1bffffh sa63111000xxxx 380000h to 38ffffh 1c0000h to 1c7fffh sa64111001xxxx 390000h to 39ffffh 1c8000h to 1cffffh sa65111010xxxx3a0000h to 3affffh1d 0000h to 1d7fffh
mb84vd2218xea/h/2219xea/h -70/85/90 28 (continued) ba : bank address bank sec- tor sector address address range (byte mode) address range (word mode) bank address a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 bank 2 sa66111011xxxx3b0000h to 3bffffh1d 8000h to 1dffffh sa67111100xxxx3c00 00h to 3cffffh 1e0000h to 1e7fffh sa68111101xxxx3d00 00h to 3dffffh 1e8000h to 1effffh sa69111110xxxx3e0000h to 3effffh1f 0000h to 1f7fffh sa70111111xxxx3f00 00h to 3fffffh 1f8000h to 1fffffh
mb84vd2218xea/h/2219xea/h -70/85/90 29 sector group addresses table (mb84vd2218xea/h) (top boot block) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000xxx sa0 sga1 0000 01 xxx sa1 to sa3 10 11 sga2 0 0 0 1xxxxx sa4 to sa7 sga3 0 0 1 0xxxxxsa8 to sa11 sga4 0 0 1 1xxxxxsa12 to sa15 sga5 0 1 0 0xxxxxsa16 to sa19 sga6 0 1 0 1xxxxxsa20 to sa23 sga7 0 1 1 0xxxxxsa24 to sa27 sga8 0 1 1 1xxxxxsa28 to sa31 sga9 1 0 0 0xxxxxsa32 to sa35 sga10 1 0 0 1xxxxxsa36 to sa39 sga11 1 0 1 0xxxxxsa40 to sa43 sga12 1 0 1 1xxxxxsa44 to sa47 sga13 1 1 0 0xxxxxsa48 to sa51 sga14 1 1 0 1xxxxxsa52 to sa55 sga15 1 1 1 0xxxxxsa56 to sa59 sga16 1 1 1 1 00 x x x sa60 to sa62 01 10 sga17 111111000 sa63 sga18 111111001 sa64 sga19 111111010 sa65 sga20 111111011 sa66 sga21 111111100 sa67 sga22 111111101 sa68 sga23 111111110 sa69 sga24 111111111 sa70
mb84vd2218xea/h/2219xea/h -70/85/90 30 sector group addresses table (mb84vd2219xea/h) (bottom boot block) sector group a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 000000000 sa0 sga1 000000001 sa1 sga2 000000010 sa2 sga3 000000011 sa3 sga4 000000100 sa4 sga5 000000101 sa5 sga6 000000110 sa6 sga7 000000111 sa7 sga8 0000 01 x x x sa8 to sa10 10 11 sga9 0 0 0 1xxxxxsa11 to sa14 sga10 0 0 1 0xxxxxsa15 to sa18 sga11 0 0 1 1xxxxxsa19 to sa22 sga12 0 1 0 0xxxxxsa23 to sa26 sga13 0 1 0 1xxxxxsa27 to sa30 sga14 0 1 1 0xxxxxsa31 to sa34 sga15 0 1 1 1xxxxxsa35 to sa38 sga16 1 0 0 0xxxxxsa39 to sa42 sga17 1 0 0 1xxxxxsa43 to sa46 sga18 1 0 1 0xxxxxsa47 to sa50 sga19 1 0 1 1xxxxxsa51 to sa54 sga20 1 1 0 0xxxxxsa55 to sa58 sga21 1 1 0 1xxxxxsa59 to sa62 sga22 1 1 1 0xxxxxsa63 to sa66 sga23 1 1 1 1 00 x x x sa67 to sa69 01 10 sga24 111111xxx sa70
mb84vd2218xea/h/2219xea/h -70/85/90 31 flash memory autoselect codes table *1 : a -1 is for byte mode. *2 : output 01h at protected sector address and output 00h at unprotected sector address. type a 12 to a 19 a 6 a 1 a 0 a- 1 * 1 code (hex) manufacturers code x v il v il v il v il 04h device code mb84vd22182ea mb84vd22182eh byte xv il v il v ih v il 55h word x 2255h mb84vd22192ea mb84vd22192eh byte xv il v il v ih v il 56h word x 2256h mb84vd22183ea mb84vd22183eh byte xv il v il v ih v il 50h word x 2250h mb84vd22193ea mb84vd22193eh byte xv il v il v ih v il 53h word x 2253h mb84vd22184ea mb84vd22184eh byte xv il v il v ih v il 5ch word x 225ch mb84vd22194ea mb84vd22194eh byte xv il v il v ih v il 5fh word x 225fh sector group protect sector group address v il v ih v il v il 01h* 2
mb84vd2218xea/h/2219xea/h -70/85/90 32 flash memory command definitions table (continued) command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data read/reset * 1 1 xxxh f0h ?? ? ??????? read/reset * 1 word 3 555h aah 2aah 55h 555h f0h ra rd ???? byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h (ba) 555h 90h ?????? byte aaah 555h (ba) aaah program word 4 555h aah 2aah 55h 555h a0h pa pd ???? byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aaah sector erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h sector erase suspend 1bab0h ?? ? ??????? sector erase resume 1 ba 30h ?? ? ??????? set to fast mode word 3 555h aah 2aah 55h 555h 20h ?????? byte aaah 555h aaah fast program * 2 word 2 xxxh a0h pa pd ? ??????? byte reset from fast mode * 2 word 2 ba 90h xxxh f0h * 6 ? ??????? byte extended sector group protection * 3 word 4 xxxh 60h spa 60h spa 40h spa sd ???? byte query * 4 word 1 (ba) 55h 98h ?? ? ??????? byte (ba) aah hi-rom entry word 3 555h aah 2aah 55h 555h 88h ?????? byte aaah 555h aaah hi-rom program * 5 word 4 555h aah 2aah 55h 555h a0h pa pd ???? byte aaah 555h aaah
mb84vd2218xea/h/2219xea/h -70/85/90 33 (continued) *1: both read/reset commands are functionally equivalent, resetting the device to the read mode. *2: this command is valid during fast mode. *3: this command is valid while reset = v id . *4: valid address is a 6 to a 0 . *5: this command is valid during hi-rom mode. *6: the data 00h is also acceptable. note : the command combinations not described in command definitions are illegal. address bits a 20 to a 11 = x = h or l for all address commands except for program address (pa) , sector address (sa) , and bank address (ba) . bus operations are defined in n device bus operation user bus operations table. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. ba = bank address (a 20 to a 15 ) spa = sector group address to be protected. set sector group address (spa) and (a 6 , a 1 , a 0 ) = (0, 1, 0) . hra = address of the hidden-rom area. mb84vd2218xea/h (top boot type) word mode : 1f8000h to 1fffffh byte mode : 3f0000h to 3fffffh mb84vd2219xea/h (bottom boot type) word mode : 000000h to 007fffh byte mode : 000000h to 00ffffh hrba = bank address of the hidden-rom area mb84vd2218xea/h (top boot type) : a 20 = a 19 = a 18 = a 17 = a 16 = a 15 = 1 mb84vd2219xea/h (bottom boot type) : a 20 = a 19 = a 18 = a 17 = a 16 = a 15 = 0 rd = data read from location ra during read operation. pd = data to be programmed at location pa. sd = sector protection verify data. output 01h at protected sector addresses and output 00h at unprotectedsector addresses. the system should generate the following address patterns : word mode : 555h or 2aah to addresses a 10 to a 0 byte mode : aaah or 555h to addresses a 10 to a 0 and a- 1 command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data hi-rom erase * 5 word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h hra 30h byte aaah 555h aaah aaah 555h hi-rom exit * 5 word 4 555h aah 2aah 55h (hrba) 555h 90h xxxh 00h ???? byte aaah 555h (hrba) aaah
mb84vd2218xea/h/2219xea/h -70/85/90 34 n n n n absolute maximum ratings *1 : voltage is defined on the basis of v ss = gnd = 0 v. *2 : minimum dc voltage on input or i/o pins is - 0.3 v. during voltage transitions, input or i/o pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f + 0.3 v or v cc s + 0.4 v. during voltage transitions, input or i/o pins may overshoot to v cc f + 2.0 v or v cc s + 2.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on reset pin is - 0.5 v. during voltage transitions, reset pin may undershoot v ss to - 2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in -v cc f or v cc s) does not exceed 9.0 v. maximum dc input voltage on reset pin is + 13.0 v which may overshoot to + 14.0 v for periods of up to 20 ns. *4 : minimum dc input voltage on wp /acc pin is - 0.5 v.during voltage transitions, wp /acc pin may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is + 10.5 v which may overshoot to + 12.0 v for periods of up to 20 ns, when v cc f is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n n n n recommended operating conditions notes : voltage is defined on the basis of vss = gnd = 0 v. operating ranges define those limits between which the functionality of the device is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 25 + 85 c voltage with respect to ground all pins except reset and wp /acc* 2 v in , v out - 0.3 v cc f + 0.3 v v cc s + 0.4 v v cc f/v cc s supply* 1 v cc f, v cc s - 0.3 + 4.0 v reset * 1, * 3 v in - 0.5 + 13.0 v wp /acc* 1, * 4 v acc - 0.5 + 10.5 v parameter symbol value unit min max ambient temperature t a - 25 + 85 c v cc f/v cc s supply voltages v cc f, v cc s + 2.7 + 3.3 v
mb84vd2218xea/h/2219xea/h -70/85/90 35 n n n n dc characteristics (continued) parameter symbol test conditions value unit min typ max input leakage current i li v in = v ss to v cc - 1.0 ?+ 1.0 m a output leakage current i lo v out = v ss to v cc - 1.0 ?+ 1.0 m a reset inputs leakage current i lit v cc = v cc max, reset = 12.5 v ?? 35 m a acc input leakage current i lia v cc = v cc max, wp /acc = v acc max ?? 20 ma flash v cc active current (read) * 1 i cc1 f ce f = v il , oe = v ih t cycle = 5 mhz byte ?? 16 ma t cycle = 5 mhz word ?? 18 t cycle = 1 mhz byte ?? 7 ma t cycle = 1 mhz word ?? 7 flash v cc active current (program/erase) * 2 i cc2 f ce f = v il , oe = v ih ?? 35 ma flash v cc active current (read-while-program) * 5 i cc3 fce f = v il , oe = v ih byte ?? 51 ma word ?? 53 flash v cc active current (read-while-erase) * 5 i cc4 fce f = v il , oe = v ih byte ?? 51 ma word ?? 53 flash v cc active current (erase-suspend-program) i cc5 fce f = v il , oe = v ih ?? 35 ma sram v cc active current i cc1 s v cc s = v cc max, ce1 s = v il , ce2s = v ih t cycle = 10 mhz ?? 40 ma sram v cc active current i cc2 s ce1 s = 0.2 v, ce2s = v cc s - 0.2 v, t cycle = 10 mhz ?? 40 ma t cycle = 1 mhz ?? 8ma flash v cc standby current i sb1 f v cc f = v cc max, ce f = v cc f 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v ? 15 m a flash v cc standby current (reset ) i sb2 f v cc f = v cc max, reset = v ss 0.3 v, wp /acc = v cc f 0.3 v ? 15 m a flash v cc current (automatic sleep mode) * 3 i sb3 f v cc f = v cc max, ce f = v ss 0.3 v reset = v cc f 0.3 v, wp /acc = v cc f 0.3 v v in = v cc f 0.3 v or v ss 0.3 v ? 15 m a sram v cc standby current i sb1 sce1 s 3 v cc s - 0.2 v, ce2s 3 v cc s - 0.2 v ?? 7 m a sram v cc standby current i sb2 sce2s 0.2 v ?? 7 m a
mb84vd2218xea/h/2219xea/h -70/85/90 36 (continued) *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when addresses remain stable for 150 ns. *4: applicable for only v cc applying. *5: embedded algorithm (program or erase) is in progress. (@5 mhz) *6: v cc indicates the lower voltage of v cc f or v ccs . parameter symbol test conditions value unit min typ max input low level v il ?- 0.3 ? 0.5 v input high level v ih ? 2.4 ? v cc * 6 + 0.3 v voltage for sector protection, and temporary sector unprotection (reset ) * 4 v id ? 11.5 ? 12.5 v voltage for program acceleration (wp /acc) * 4 v acc ? 8.5 9.0 9.5 v output low voltage level v ol v cc f = v cc s = v cc min, i ol = 1.0 ma ?? 0.4 v output high voltage level v oh v cc f = v cc s = v cc min, i oh = - 0.5 ma 2.4 ?? v flash low v cc lock-out voltage v lko ? 2.3 ? 2.5 v
mb84vd2218xea/h/2219xea/h -70/85/90 37 n n n n ac characteristics ? ce timing ? timing diagram for alternating sram to flash parameter symbol test setup value unit jedec standard min ce recover time ? t ccr ? 0ns t ccr t ccr cef ce1s t ccr t ccr ce2s
mb84vd2218xea/h/2219xea/h -70/85/90 38 ? read only operations characteristics (flash) test conditions: output load : 1 ttl gate and 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v or 3.0 v timing measurement reference level input : 0.5 v cc f output : 0.5 v cc f parameter symbol test setup value unit 70 85 90 jedec standard min max min max min max read cycle time t avav t rc ? 70 ? 85 ? 90 ? ns address to output delay t avqv t acc ce f = v il oe = v il ? 70 ? 85 ? 90 ns chip enable to output delay t elqv t ce oe = v il ? 70 ? 85 ? 90 ns output enable to output delay t glqv t oe ?? 30 ? 35 ? 40 ns chip enable to output high-z t ehqz t df ?? 25 ? 30 ? 30 ns output enable to output high-z t ghqz t df ?? 25 ? 30 ? 30 ns output hold time from addresses, ce f or oe , whichever occurs first t axqx t oh ? 0 ? 0 ? 0 ? ns reset pin low to read mode ? t ready ?? 20 ? 20 ? 20 m s
mb84vd2218xea/h/2219xea/h -70/85/90 39 ? read cycle (flash) ? hardware reset/read operation timing diagram (flash) address cef oe we dq output valid address stable t rc t acc t oe t df t ce high-z high-z t oeh address reset dq output valid address stable t rc t acc t oh t rp t rh t ce t rh high-z cef
mb84vd2218xea/h/2219xea/h -70/85/90 40 ? erase/program operations (flash) (continued) parameter symbol value value value unit 70 85 90 jedec standard min typ max min typ max min typ max write cycle time t avav t wc 70 ?? 85 ?? 90 ?? ns address setup time (we to addr.) t avwl t as 0 ?? 0 ?? 0 ?? ns address setup time to cef low during toggle bit polling ? t aso 12 ?? 15 ?? 15 ?? ns address hold time (we to addr.) t wlax t ah 45 ?? 45 ?? 45 ?? ns address hold time from cef or oe high during toggle bit polling ? t aht 0 ?? 0 ?? 0 ?? ns data setup time t dvwh t ds 30 ?? 35 ?? 35 ?? ns data hold time t whdx t dh 0 ?? 0 ?? 0 ?? ns output enable setup time ? t oes 0 ?? 0 ?? 0 ?? ns output enable hold time read ? t oeh 0 ?? 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? 10 ?? ns cef high during toggle bit polling ? t ceph 20 ?? 20 ?? 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? 20 ?? 20 ?? ns read recover time before write (oe to ce f) t ghel t ghel 0 ?? 0 ?? 0 ?? ns read recover time before write (oe to we ) t ghwl t ghwl 0 ?? 0 ?? 0 ?? ns we setup time (ce f to we ) t wlel t ws 0 ?? 0 ?? 0 ?? ns cef setup time (we to ce f) t elwl t cs 0 ?? 0 ?? 0 ?? ns we hold time (ce f to we ) t ehwh t wh 0 ?? 0 ?? 0 ?? ns cef hold time (we to ce f) t wheh t ch 0 ?? 0 ?? 0 ?? ns write pulse width t wlwh t wp 35 ?? 35 ?? 35 ?? ns ce f pulse width t eleh t cp 35 ?? 35 ?? 35 ?? ns write pulse width high t whwl t wph 25 ?? 30 ?? 25 ?? ns cef pulse width high t ehel t cph 25 ?? 30 ?? 25 ?? ns byte programming operation t whwh1 t whwh1 ? 8 ?? 8 ?? 8 ?m s word programming operation ? 12 ?? 16 ?? 16 ?m s sector erase operation * 1 t whwh2 t whwh2 ? 0.2 ?? 1 ?? 1 ? s
mb84vd2218xea/h/2219xea/h -70/85/90 41 (continued) *1: this does not include the preprogramming time. *2: this timing is for sector protection operation. *3: the time between writes must be less than t tow otherwise that command will not be accepted and erasure will start. a time-out or t tow from the rising edge of last cef or we whichever happens first will initiate the execution of the sector erase command (s) . *4: when the erase suspend command is written during the sector erase operation, the device will take maximum of t spd to suspend the erase operation. parameter parameter symbol value unit 70 85 90 jedec standard min typ max min typ max min typ max v cc f setup time ? t vcs 50 ?? 50 ?? 50 ??m s voltage transition time * 2 ? t vlht 4 ?? 4 ?? 4 ??m s rise time to v id * 2 ? t vidr 500 ?? 500 ?? 500 ?? ns rise time to v acc ? t vaccr 500 ?? 500 ?? 500 ?? ns recover time from ry/by ? t rb 0 ?? 0 ?? 0 ?? ns reset pulse width ? t rp 500 ?? 500 ?? 500 ?? ns delay time from embedded output enable ? t eoe ?? 70 ?? 85 ?? 90 ns reset hold time before read ? t rh 200 ?? 200 ?? 200 ?? ns program/erase valid to ry/by delay ? t busy ?? 90 ?? 90 ?? 90 ns erase time-out time * 3 ? t tow 50 ?? 50 ?? 50 ??m s erase suspend transition time * 4 ? t spd ?? 20 ?? 20 ?? 20 m s
mb84vd2218xea/h/2219xea/h -70/85/90 42 ? write cycle (we control) (flash) address we oe cef data 3rd bus cycle 555h a0h pd dq 7 d out d out pa pa data polling t wc t cs t wp t ds t dh t oh t oe t ce t wph t whwh1 t ghwl t ch t as t ah t rc t df notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode (the addresses differ from 8 mode.)
mb84vd2218xea/h/2219xea/h -70/85/90 43 ? write cycle (ce f control) (flash) address we oe cef data 3rd bus cycle 555h a0h pd dq 7 d out pa pa data polling t wc t ws t cp t ds t dh t cph t whwh1 t ghel t wh t as t ah notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence.
mb84vd2218xea/h/2219xea/h -70/85/90 44 ? write cycle (ce f control) (flash) address we oe cef data 3rd bus cycle 555h a0h pd dq 7 d out pa pa data polling t wc t ws t cp t ds t dh t cph t whwh1 t ghel t wh t as t ah notes : pa is address of the memory location to be programmed. pd is data to be programmed at byte address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates the last two bus cycles out of four bus cycle sequence. these waveforms are for the 16 mode (the addresses differ from 8 mode.)
mb84vd2218xea/h/2219xea/h -70/85/90 45 ? ac waveforms chip/sector erase operations (flash) 555h 2aah 2aah 555h 555h t wc t ghwl t as t ah sa * address we oe cef dq v cc f t cs t ch t vcs t wph t wp t ds t dh aah 55h 80h aah 55h 10h/ 30h 30h for sector erase * : sa is the sector address for sector erase. addresses = 555h for chip erase. note : these waveform are for the 16 mode (the addresses differ from 8 mode.)
mb84vd2218xea/h/2219xea/h -70/85/90 46 ? ac waveforms for data polling during embedded algorithm operations (flash) we oe cef dq 7 dq 6 to dq 0 ry/by data data dq 7 = valid data dq 0 to dq 6 valid data t eoe dq 7 dq 0 to dq 6 = output flag t ch t oe t df t oeh t ce t whwh1 or 2 high-z high-z * t busy * : dq 7 = valid data (the device has completed the embedded operation.)
mb84vd2218xea/h/2219xea/h -70/85/90 47 ? ac waveforms for toggle bit during embedded algorithm operations (flash) we cef address oe dq 6 /dq 2 ry/by data t busy t aht t aht t aso t ceph t as t oeh t oeh t ce t dh t oe t oeph * toggle data toggle data toggle data stop toggling output valid * : dq 6 stops toggling (the device has completed the embedded operation) .
mb84vd2218xea/h/2219xea/h -70/85/90 48 ? bank-to-bank read/write timing diagram (flash) address we oe cef dq ba1 ba1 ba1 read valid output valid output valid intput valid intput valid output status ba2 (555h) ba2 (pa) ba2 (pa) t df t dh t ds t oe t ghwl t as t aht t as t acc t ce t wp t rc t ceph read t rc command t wc read t rc command t wc read t rc t ah t df (pd) (a0h) t oeh note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1 : address corresponding to bank 1. ba2 : address corresponding to bank 2.
mb84vd2218xea/h/2219xea/h -70/85/90 49 ? ry/by timing diagram during write/erase operations (flash) ? reset , ry/by timing diagram (flash) rising edge of the last write pulse entire programming or erase operations t busy ry/by we cef ry/by reset we t ready t rp t rb
mb84vd2218xea/h/2219xea/h -70/85/90 50 ? temporary sector group unprotection (flash) cef ry/by reset v cc f v ih we v id program or erase command sequence unprotection period t vcs t vidr t vlht t vlht t vlht
mb84vd2218xea/h/2219xea/h -70/85/90 51 ? extended sector group protection (flash) v cc f reset address a 6 , a 0 a 1 cef data 60h 60h 40h 01h 60h t vcs t vidr t vlht time - out t wp t oe spax spax spay oe we t wc t wc spax : sector group address to be protected spay : next group sector address to be protected time-out : time-out window = 250 m s (min)
mb84vd2218xea/h/2219xea/h -70/85/90 52 ? accelerated program (flash) cef ry/by wp/acc v cc f v ih we v acc acceleration period t vcs t vaccr t vlht t vlht t vlht program command sequence
mb84vd2218xea/h/2219xea/h -70/85/90 53 ? read cycle (sram) test conditions - output load : 1 ttl gate and 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v or v cc s timing measurement reference level input : 0.5 v cc s output : 0.5 v cc s parameter symbol value unit 70 85 90 minmaxminmaxminmax read cycle time t rc 70 ? 85 ? 85 ? ns address access time t aa ? 70 ? 85 ? 85 ns chip enable (ce1 s) access time t co1 ? 70 ? 85 ? 85 ns chip enable (ce2s) access time t co2 ? 70 ? 85 ? 85 ns output enable access time t oe ? 35 ? 45 ? 45 ns lb s, ub s to output valid t ba ? 70 ? 85 ? 85 ns chip enable (ce1 s low and ce2s high) to output active t coe 5 ? 5 ? 5 ? ns output enable low to output active t oee 0 ? 0 ? 0 ? ns ub s, lb s enable low to output active t be 0 ? 0 ? 0 ? ns chip enable (ce1 s high or ce2s low) to output high-z t od ? 25 ? 35 ? 35 ns output enable high to output high-z t odo ? 25 ? 35 ? 35 ns ub s, lb s output enable to output high-z t bd ? 25 ? 35 ? 35 ns output data hold time t oh 10 ? 10 ? 10 ? ns
mb84vd2218xea/h/2219xea/h -70/85/90 54 ? read cycle (sram) address oe ce2s ce1s lb s , ub s dq t rc t oh t od t od t odo t bd t aa t co1 t co2 t oe t oee t ba t be t coe t coe valid data out note : we remains h during the read cycle.
mb84vd2218xea/h/2219xea/h -70/85/90 55 ? write cycle (sram) parameter symbol value unit 70 85 90 min max min max min max write cycle time t wc 70 ? 85 ? 85 ? ns write pulse width t wp 55 ? 60 ? 60 ? ns chip enable to end of write t cw 60 ? 70 ? 70 ? ns address valid to end of write t aw 60 ? 70 ? 70 ? ns ub s, lb s to end of write t bw 60 ? 70 ? 70 ? ns address setup time t as 0 ? 0 ? 0 ? ns write recovery time t wr 0 ? 0 ? 0 ? ns we low to output high-z t odw ? 25 ? 35 ? 35 ns we high to output active t oew 0 ? 0 ? 0 ? ns data setup time t ds 30 ? 35 ? 35 ? ns data hold time t dh 0 ? 0 ? 0 ? ns
mb84vd2218xea/h/2219xea/h -70/85/90 56 ? write cycle * 1 (we control) (sram) t wc t as t wp t wr t aw t cw t cw t bw t odw t ds t dh t oew address we ce1s ce2s d out d in *2 *3 *4 *4 valid data in lb s , ub s *1: if oe is h during the write cycle, the outputs will remain at high-z. *2: if ce1 s goes l (or ce2s goes h) coincident with or after we goes l, the output will remain at high-z. *3: if ce1 s goes h (or ce2s goes l) coincident with or before we goes h, the output will remain at high-z. *4: because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied.
mb84vd2218xea/h/2219xea/h -70/85/90 57 ? write cycle * 1 (ce1 s control) (sram) t wc t as t wp t wr t aw t cw t cw t bw t odw t ds t dh t coe t be valid data in address we ce1s ce2s d out d in *2 lb, ub *1: if oe is h during the write cycle, the outputs will remain at high-z. *2: because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied.
mb84vd2218xea/h/2219xea/h -70/85/90 58 ? write cycle * 1 (ce2s control) (sram) adrress we ce1s ce2s d out d in *2 valid data in t ds t odw t coe t be t bw t cw t cw t wp t wc t as t wr t aw t dh lb s , ub s *1: if oe is h during the write cycle, the outputs will remain at high-z. *2: because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied.
mb84vd2218xea/h/2219xea/h -70/85/90 59 ? write cycle * 1 (lb s, ub s control) (sram) address we ce1s ce2s d out d in valid data in t ds t odw t coe t be t bw t as t aw t cw t cw t wp t wc t wr t dh *2 lb s , ub s *1: if oe is h during the write cycle, the outputs will remain at high-z. *2: because i/o signals may be in the output state at this time, input signals of reverse polarity must not be applied.
mb84vd2218xea/h/2219xea/h -70/85/90 60 n n n n erase and programming performance (flash) n n n n data retention characteristics (sram) note : t rc : read cycle time ? ce1 s controlled data retention mode * 1 parameter limits unit comment min typ max sector erase time ? 110s excludes programming time prior to erasure byte programming time ? 8 300 m s excludes system-level overhead word programming time ? 16 360 m s excludes system-level overhead chip programming time ?? 100 s excludes system-level overhead erase/program cycle 100,000 ?? cycle parameter symbol value unit min typ max data retention supply voltage v dh 1.5 ? 3.3 v standby current v dh = 3.0 v i dds2 ? 1.5 7 m a chip deselect to data retention mode time t cdr 0 ?? ns recovery time t r t rc ?? ns data retention mode *2 *2 t r t cdr v ccs - 0.2 v v cc s v ih v dh ce1s 2.7 v gnd *1: in ce1 s controlled data retention mode, input level of ce2s should be fixed v cc s to v cc s - 0.2 v or v ss to 0.2 v during data retention mode. other input and input/output pins can be used between - 0.3 v to v cc s + 0.3 v. *2: when ce1 s is operating at the v ih min level, the standby current is given by i sb1 s during the transition of v cc s from 3.3 v to v ih min level.
mb84vd2218xea/h/2219xea/h -70/85/90 61 ? ce2s controlled data retention mode n n n n package pin capacitance note : test conditions t a = + 25c, f = 1.0 mhz n n n n handling of package please handle this package carefully since the sides of package are created with acute angles. n n n n caution ? the high voltage (v id ) cannot apply to address pins and control pins except reset . exception is when autoselect and sector group protection function are used, then the high voltage (v id ) can be applied to reset . ? without the high voltage (v id ) , sector group protection can be achieved by using extended sector group protection command. parameter symbol test setup value unit typ max input capacitance c in v in = 01114pf output capacitance c out v out = 01216pf control pin capacitance c in2 v in = 01416pf wp /acc pin capacitance c in3 v in = 0 21.5 26 pf 0.2 v data retention mode v cc s ce2s v dh v ih v il t cdr t r gnd 2.7 v note: in ce2s controlled data retention mode, input and input/output pins can be used between - 0.3 v to v cc s + 0.3 v.
mb84vd2218xea/h/2219xea/h -70/85/90 62 n n n n ordering information mb84vd2218 x ea -85 pbs package type pbs = 71-ball bga speed option device revision (valid combination) ea eh bank size 2 = 4 mbit / 28 mbit 3 = 8 mbit / 24 mbit 4 = 16 mbit / 16 mbit device number/description 32 mega-bit (4 m 8-bit or 2 m 16-bit) dual operation flash memory 3.0 v-only read, program, and erase 4 mega-bit (512 k 8-bit or 256 k 16-bit) sram boot code sector architecture 84vd2218 = top sector 84vd2219 = bottom sector
mb84vd2218xea/h/2219xea/h -70/85/90 63 n n n n package dimension 71-ball plastic bga (bga-71p-m02) dimensions in mm (inches). c 2000 fujitsu limited b71002s-1c-1 11.00?.10(.433?004) 7.00?.10 (.276?004) index-mark area 0.10(.004) 0.38?.10 (.015?004) (stand off) .041 ?004 +.006 ?.10 +0.15 1.05 (mounting height) 0.80 (.031) 5.60(.220)ref 7.20(.283) 8.80(.346) 0.80 (.031) 5.60(.220) ref a b c d e f g h j k l m 1 2 3 4 5 6 7 8 71-.018 ?002 +.004 ?.05 +0.10 71-0.45 m 0.08(.003)
mb84vd2218xea/h/2219xea/h -70/85/90 fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0204 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.

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